A device having thin first spacers and partially recessed thick second spacers for improved salicide resistance on polysilicon gates

ABSTRACT

A method and device for improved salicide resistance in polysilicon gates under 0.20 μm. The several embodiments of the invention provide for formation of gate electrode structures with recessed and partially recessed spacers. One embodiment, provides a gate electrode structure with recessed thick inner spacers and thick outer spacers. Another embodiment provides a gate electrode structure with recessed thin inner spacers and recessed thick outer spacers. Another embodiment provides a gate electrode structure with thin inner spacers and partially recessed outer spacers. Another embodiment provides a gate electrode structure with two spacer stacks. The outermost spacer stack with recessed thin inner spacers and recessed thick outer spacers. The inner spacer stack with thin inner spacers and thin outer spacers. Another embodiment provides a gate electrode structure with two spacer stacks. The outermost spacer stack with recessed thin inner spacers and recessed thick outer spacers. The inner spacer stack with recessed thin inner spacers and recessed thin outer spacers.

FIELD OF THE INVENTION

[0001] The present invention relates to the field of semiconductordevices. More particularly, the present invention relates to a methodand device for improved resistance on gate electrodes. Specifically, thepresent invention relates to a method and device for improved salicideresistance on polysilicon gates.

BACKGROUND OF THE INVENTION

[0002] Transistors are commonly used in semiconductor circuitry tocontrol current flow. For example, a transistor can be used as aswitching mechanism to allow the flow of current between a source and adrain region in a circuit when a certain threshold voltage is met.Transistors generally include a gate electrode that allows or preventsthe flow of current in the transistor based on applied voltage.

[0003]FIG. 1a shows a cross-sectional view of a conventional gateelectrode 100 formed on a substrate 110, the underlying structure ofwhich is not shown. It should be noted that the figures are merelyillustrative and have been simplified for clarity purposes. A thininsulative layer 120 is formed on the substrate 110 to act as a barrierbetween the substrate 110 and the conductive portions of the gateelectrode 100. An example of an insulative layer 120 can be an oxidelayer, such as silicon dioxide (SiO₂). Formed on the insulative layer120 is a gate layer 130. An example of a gate layer 130 can be apolysilicon layer. Formed on the gate layer 130 is a conductive layer160. An example of a conductive layer 160 can be a polycide layer, suchas titanium salicide (TiSi₂). When a threshold voltage is applied to thegate layer 130 by the conductive layer 160, current will flow throughthe gate layer 130. Often insulative spacers 140 and 150 are formed toeach side of the gate layer 130 to prevent transfer of current betweenthe gate layer 130 and surrounding structures in the semiconductor.

[0004] In semiconductor circuit design, frequently, gate electrodes aredesigned in long continuous lines on the semiconductor substrate toefficiently provide current to several transistors in a circuit.Currently, improved semiconductor transistor performance is beingachieved through device scaling in which the gate layer widths are beingreduced from 0.20 μm to 0.15 μm and below (sub-0.15 μm). As the gatelayer width dimensions decrease, so do the conductive layer line widthsformed above them.

[0005] When the gate layer widths decrease below 0.20 μm, currentprocess techniques produce conductive lines with sharply increasingresistance. This is detrimental to the efficiency of the semiconductor,as higher resistance decreases the speed of the semiconductor circuitry.Additionally, process yields drop due to defective conductive lineformation reducing manufacturing output. These problems have beenparticularly noted in current fabrication processes where titaniumsalicide (TiSi₂) is formed as the conductive layer in a polysilicongate.

[0006]FIG. 1b illustrates a cross-sectional view of a conventional gateelectrode 100 formed on a substrate 110, the underlying structure ofwhich is not shown. An example of a gate electrode 100 can be apolysilicon gate electrode. Formed on the substrate 110 is an insulativelayer 120. An example of an insulative layer 120 can be an oxide. Formedon the insulative layer 120 is a conductive gate layer 130. An exampleof a gate layer 130 is a polysilicon layer. Formed on the gate layer 130is a conductive layer 160. An example of a conductive layer 160 can be apolycide, such as titanium salicide. Insulative spacers 140 and 150 areformed adjacent to the gate layer 130 and conductive layer 160 toprevent current flow between the gate layer 100 and surroundingstructures.

[0007] During formation of the conductive layer 160, components fromunderlying gate layer 130 often out diffuse into a reactant layer thatis used to form the conductive layer 160. For example, siliconcomponents of an underlying gate layer 130 may out diffuse into theconductive layer 160. This out diffusion results in a conductive layer160 wider than the gate layer 130. When the gate layer 100 width isdecreased below 0.20 μm, the conductive layer 160 becomes stressed byits enclosure between the side walls of the spacers 140. This results inincreased resistance in the conductive layer 160. Increased resistancein the conductive layer directly impacts the quality of thesemiconductor circuit. The circuit becomes inefficient and circuitfailure or device failure may occur.

[0008] Another result of decreasing the gate line widths below 0.20 μmis a decrease in process yields. This is due to non-formation of theconductive layer. This is attributed to the reduced reaction area, ornucleation sites, available at such small dimensions. The reduceddimensions of the gate layer reduces nucleation sites on which theconductive layer can form during processing. Using current processtechniques, if sufficient nucleation sites are not provided, theconductive layer often won't form. This directly impacts thesemiconductor manufacturer by reducing output.

[0009] Based on the above described problems, it would be desirable tohave a method and/or device which will improve the polycide resistancein polysilicon gate widths below 0.20 μm.

BRIEF SUMMARY OF THE INVENTION

[0010] The present invention provides a method and a device whichimproves polycide resistance in gate electrode widths below 0.20 μm. Theinvention provides several embodiments one embodiment of which isdescribed below.

[0011] In one embodiment of the present invention there is provided agate electrode comprising a thin insulative layer. A gate layer isformed on the thin insulative layer. A conductive layer is formed on thegate layer. Thick first spacers are formed adjacent to opposite sides ofthe gate layer. Thick second spacers are formed adjacent to the thickfirst spacers. The thick first spacers are recessed to create an openspace between the gate layer and thick second spacers.

BRIEF DISCUSSION OF THE SEVERAL VIEWS OF THE DRAWINGS

[0012] For fuller understanding of the present invention, reference ismade to the accompanying drawings in the following detailed descriptionof the invention. In the drawings:

[0013]FIG. 1(a) is a cross-sectional illustration of a conventional gateelectrode in the prior art depicting a non-stressed conductive layer.

[0014]FIG. 1(b) is a cross-sectional illustration of a conventional gateelectrode in the prior art depicting a stressed conductive layer.

[0015] FIGS. 2 (a)-(h) are cross-sectional illustrations of theformation of a gate electrode with a conductive layer and recessed thickinner spacers and non-recessed thick outer spacers.

[0016] FIGS. 3 (a)-(i) are cross-sectional illustrations of theformation of a gate electrode with a conductive layer and recessed thininner spacers and recessed thick outer spacers.

[0017] FIGS. 4 (a)-(i) are cross-sectional illustrations of theformation of a gate electrode with a conductive layer and non-recessedthin inner spacers and partially recessed outer spacers.

[0018] FIGS. 5 (a)-(m) are cross-sectional illustrations of theformation of a gate electrode with a conductive layer and two spacerstacks. The outermost spacer stack having recessed thin inner spacersand recessed thick outer spacers. The inner spacer stack havingnon-recessed thin inner spacers and non-recessed thin outer spacers.

[0019] FIGS. 6 (a)-(p) are cross-sectional illustrations of theformation of a gate electrode with a conductive layer and two spacerstacks. The outermost spacer stack having recessed thin inner spacersand recessed thick outer spacers. The inner spacer stack having recessedthin inner spacers and recessed thin outer spacers.

DETAILED DESCRIPTION OF THE INVENTION

[0020] The present invention provides a method and a device to improvepolycide resistance on gate electrodes less than 0.20 μm in width. Inthe following description of the several embodiments of the invention,numerous details are set forth in order to provide a thoroughunderstanding of the present invention. It will be appreciated by onehaving ordinary skill in the art that the present invention may bepracticed without such specific details. In other instances, well knownstructures and techniques have not been described in detail in order toavoid obscuring the subject matter of the present invention. It will beunderstood by those having ordinary skill in the art that the structuresof the present invention may be formed by various techniques.

[0021] Referring now to the drawings, one embodiment of the presentinvention is shown in FIGS. 2a-h. FIG. 2a illustrates a gate layer 220formed on a thin insulative layer 210 on a substrate 200. In oneembodiment, the gate layer 220 can be a polysilicon. In one embodiment,the gate layer 220 is less than 0.20 μm in width. These structures areformed using conventional deposition and etching techniques well-knownin the art.

[0022] In FIG. 2b; a thick first spacer layer 230 is deposited or grownon the gate layer 220 and substrate 200. In one embodiment, the thickfirst spacer layer 230 can be an oxide. In one embodiment, the thickfirst spacer layer 230 can be deposited or grown to a thickness in therange of approximately 200-600Å, for example, 300 Å. It should be notedthat the thick first spacer layer 230 can be deposited or grown usingdeposition techniques that are well known in the art and are notdescribed in detail herein.

[0023] In FIG. 2c, a thick second spacer layer 240 is deposited or grownon the thick first spacer layer 230. In one embodiment, the thick secondspacer layer 240 can be a nitride. In one embodiment, the thick secondspacer layer 240 can be deposited or grown to a thickness in the rangeof approximately 300-2000 Å, for example, 800 Å. It should be noted thatthe thick second spacer layer 240 can be deposited or grown usingdeposition techniques that are well known in the art and are notdescribed in detail herein.

[0024] The thick second spacer layer 240 is etched to form the spacerstructure illustrated in FIG. 2d. In one embodiment, this etch is ananisotropic (directional) etch which will remove nitride, but not oxide.Examples of anisotropic etches are a dry etch or a plasma etch.

[0025] The thick first spacer layer 230 is recessed by etching to formthe spacer structure illustrated in FIG. 2e. The recessing creates anopen space between the thick second spacer layer 240 and the gate layer220. In one embodiment, the thick-first spacer layer 230 is etchedapproximately 60 nm deeper than the surface of the gate layer 220. Inone embodiment, the etching forms a space approximately 200-600 Å, forexample, 300 Å, between the thick second spacer layer 240 and the gatelayer 220. In one embodiment this etch is an isotropic(multidirectional) etch which will remove oxide, but not nitride.Examples of isotropic etches are dry or wet etches. It should be notedthat the side walls of the gate layer 220 are now exposed creating alarger contact (reaction) surface area.

[0026] In FIG. 2f, a reactant layer 250 is deposited, for example bysputter, electron beam evaporation, chemical vapor, or plasmadeposition. In one embodiment, the reactant layer 250 can be a metal,such as titanium.

[0027] The reactant layer 250 and the gate layer 220 are then annealedto form a conductive layer 260 as shown in FIG. 2g. In one embodiment,the formed conductive layer 260 can be a polycide, such as titaniumsalicide. In one embodiment, the anneal may be performed using a rapidthermal annealing process in a nitrogen ambient. In one embodiment,additional anneals can be performed to decrease the resistance of theconductive layer 260. It is to be noted that the conductive layer 260can now extend beyond the edges of the gate layer 220 and is notconstrained and stressed by the thick first spacer layer 230.

[0028] The unreacted portion of reactant layer 250 is etched awayleaving the conductive layer 260 as illustrated in FIG. 2h. In oneembodiment, this etch is an isotropic etch which will remove unreactedtitanium, but not titanium salicide.

[0029] Another embodiment of the present invention is illustrated inFIGS. 3a -i. FIG. 3a illustrates a gate layer 320 formed on a thininsulative layer 310 on a substrate 300. In one embodiment, the gatelayer 320 can be a polysilicon. In one embodiment, the gate layer 320 isless than 0.20 μm in width. These structures are formed usingconventional deposition and etching techniques well-known in the art.

[0030] In FIG. 3b, a thin first spacer layer 330 is deposited or grownon the gate layer 320 and substrate 300. In one embodiment, the thinfirst spacer layer 330 can be an oxide. In one embodiment, the thinfirst spacer layer 330 is deposited or grown to a thickness in the rangeof approximately 50-300 Å, for example, 100 Å. It should be noted thatthe thin first spacer layer 330 can be deposited or grown usingdeposition techniques that are well known in the art and are notdescribed in detail herein.

[0031] In FIG. 3c, a thick second spacer layer 340 is deposited or grownon the thin first spacer layer 330. In one embodiment, the thick secondspacer layer 340 can be a nitride. In one embodiment, the thick secondspacer layer 340 is deposited or grown to a thickness in the range ofapproximately 300-2000 Å, for example, 800 Å. It should be noted thatthe thick second spacer layer 340 can be deposited or grown usingdeposition techniques that are well known in the art and are notdescribed in detail herein.

[0032] The thick second spacer layer 340 is etched a first time to formthe structure illustrated in FIG. 3d. In one embodiment, this etch is ananisotropic (directional) etch which will remove nitride, but not oxide.Examples of anisotropic etches are a dry etch or a plasma etch.

[0033] The thick second spacer layer 340 is then recessed by etching asecond time to form the spacer structure illustrated in FIG. 3e. In oneembodiment, the thick second spacer layer 340 is etched approximately 60nm deeper than the surface level of the gate layer 320. In oneembodiment, this etch is an isotropic (multidirectional) etch which willremove nitride, but not oxide. Examples of isotropic etches are a wet ordry etch.

[0034] The thin first spacer layer 330 is then recessed by etching toform the spacer structure illustrated in FIG. 3f. In one embodiment,this etch is an isotropic (multidirectional) etch which will removeoxide, but not nitride. Examples of isotropic etches are a dry, wet orchemical bath etch. It should further be noted that the side walls ofthe gate layer 320 are now exposed creating a larger contact (reaction)surface area

[0035] In FIG. 3g, a reactant layer 350 is deposited, for example, bysputter, electron beam evaporation, chemical vapor, or plasmadeposition. In one embodiment, the reactant layer 350 can be a metal,such as titanium.

[0036] The reactant layer 350 and the gate layer 320 are then annealedto form a conductive layer 360 as shown in FIG. 3h. In one embodiment,the formed conductive layer 360 can be a polycide, such as titaniumsalicide. In one embodiment, the anneal may be performed using a rapidthermal annealing process in a nitrogen ambient. In one embodiment,additional anneals can be performed to decrease the resistance of theconductive layer 360. It is to be noted that the conductive layer 360can now extend beyond the edges of the gate layer 320 and is notconstrained and stressed.

[0037] The unreacted portion of reactant layer 350 is etched awayleaving the conductive layer 360 as illustrated in FIG. 3i. In oneembodiment, this etch is an isotropic etch which will remove unreactedtitanium, but not titanium salicide.

[0038] Another embodiment of the present invention is illustrated inFIGS. 4a-i. FIG. 4a illustrates a gate layer 420 formed on a thininsulative layer 410 on a silicon substrate 400. In one embodiment, thegate layer 420 can be polysilicon. In one embodiment, the gate layer 420is less than 0.20 μm in width. These structures are formed usingconventional deposition and etching techniques well-known in the art.

[0039] In FIG. 4b, a thin first spacer layer 430 is deposited or grownon the gate layer 420 and substrate 400. In one embodiment, the thinfirst spacer layer 430 can be an oxide. In one embodiment, the thinfirst spacer layer 430 is deposited or grown to a thickness in the rangeof approximately 50-300 Å, for example, 100 Å. It should be noted thatthe thin first spacer layer 430 can be deposited or grown usingdeposition techniques that are well known in the art and are notdescribed in detail herein.

[0040] In FIG. 4c, a thick second spacer layer 440 is deposited or grownon the thin first spacer layer 430. In one embodiment, the thick secondspacer layer 440 can be a nitride. In one embodiment, the thick secondspacer layer 440 can be deposited or grown to a thickness in the rangeof approximately 300-2000 Å, for example, 800 Å. It should be noted thatthe thick second spacer layer 440 can be deposited or grown usingdeposition techniques that are well known in the art and are notdescribed in detail herein.

[0041] The thick second spacer layer 440 is etched a first time to formthe structure illustrated in FIG. 4d. In one embodiment, this etch is ananisotropic (directional) etch which will remove nitride, but not oxide.Examples of anisotropic etches are a dry etch or a plasma etch.

[0042] The thick second spacer layer 440 is then partially recessed byetching a second time to form the spacer structure illustrated in FIG.4e. In one embodiment, the partial recess creates a thin second spacerwall 470 adjacent to the thin first spacer layer 430. In one embodiment,the thin second spacer wall 470 can be in the range of approximately50-200 Å, for example, 100 Å, in width and can extend approximately 60nm deeper than the surface level of the gate layer 420. In oneembodiment, this etch is an anisotropic (directional) etch which willremove nitride, but not oxide. Examples of anisotropic etches are a dryetch or a plasma etch.

[0043] Following the partial recessing of the thick second spacer layer440, the thin first spacer layer 430 is etched to form the spacerstructure illustrated in FIG. 4f. In one embodiment, this etch is anisotropic (multidirectional) etch which will remove oxide, but notnitride. Examples of isotropic etches are a dry, wet or chemical bathetch.

[0044] In FIG. 4g, a reactant layer 450 is deposited, for example, bysputter, electron beam evaporation, chemical vapor, or plasmadeposition. In one embodiment, the reactant layer 450 can be a metal,such as titanium.

[0045] The reactant layer 450 and the gate layer 420 are then annealedto form a conductive layer 460 as shown in FIG. 4h. In one embodiment,the conductive layer 460 can be a polycide, such as titanium salicide.In one embodiment, the anneal may be performed using a rapid thermalannealing process in a nitrogen ambient. In one embodiment, additionalanneals can be performed to decrease the resistance of the conductivelayer 460. It is to be noted that the conductive layer 460 can nowextend beyond the edges of the gate layer 420 due to flexibility in thethin spacer walls formed from the thin first spacer layer 430 and thethin second spacer walls 470.

[0046] The unreacted portion of reactant layer 450 is etched awayleaving the conductive layer 460 as illustrated in FIG. 4i. In oneembodiment, this etch is an isotropic etch which will remove unreactedtitanium, but not titanium salicide.

[0047] Another embodiment of the present invention is illustrated inFIGS. 5a-m. FIG. 5a illustrates a gate layer 520 formed on a tininsulative layer 510 on a substrate 500. In one embodiment, the gatelayer 520 can be polysilicon. In one embodiment, the polysilicon gatelayer 520 is less than 0.20 μm in width. These structures are formedusing conventional deposition and etching techniques well-known in theart.

[0048] In FIG. 5b, a thin first spacer layer 530 is deposited or grownon the gate layer 520 and substrate 500. In one embodiment, the thinfirst spacer layer 530 can be an oxide. In one embodiment, the thinfirst spacer layer 530 is deposited or grown to a thickness in the rangeof approximately 50-150 Å, for example, 50 Å. It should be noted thatthe thin first spacer layer 530 can be deposited or grown usingdeposition techniques that are well known in the art and are notdescribed in detail herein.

[0049] In FIG. 5c, a thin second spacer layer 540 is deposited or grownon the thin first spacer layer 530. In one embodiment, the thin secondspacer layer 540 can be a nitride. In one embodiment, the thin secondspacer layer 540 can be deposited or grown to a thickness in the rangeof approximately 50 -150 Å, for example, 50 Å. It should be noted thatthe thin second spacer layer 540 can be deposited or grown usingdeposition techniques that are well known in the art and are notdescribed in detail herein.

[0050] The thin second spacer layer 540 is etched a first time to formthe structure illustrated in FIG. 5d. In one embodiment, this etch is ananisotropic (directional) etch which will remove nitride, but not oxide.Examples of anisotropic etches are a dry etch or a plasma etch.

[0051] Following the etch of the thin second spacer layer 540, the thinfirst spacer layer 530 is etched to form the structure illustrated inFIG. 5e. In one embodiment, this etch is an isotropic (multidirectional)which will remove oxide, but not nitride. Examples of isotropic etchesare dry or wet etches. It should be further noted that at this point ina process flow, implants of dopants can be added to the structure toenhance circuit performance.

[0052] In FIG. 5f, a thin third spacer layer 550 is deposited or grown.In one embodiment, the thin third spacer layer 550 can be an oxide. Inone embodiment, the thin third spacer layer 550 is deposited or grown toa thickness in the range of approximately 50-300 Å, for example, 100 Å.It should be noted that the thin third spacer layer 550 can be depositedor grown using deposition techniques that are well known in the art andare not described in detail herein.

[0053] In FIG. 5g, a thick fourth spacer layer 560 is deposited or grownon the thin third spacer layer 550. In one embodiment, the thick fourthspacer layer 560 can be a nitride. In one embodiment, the thick fourthspacer layer 560 is deposited or grown to a thickness in the range ofapproximately 300-2000 Å, for example, 800 Å. It should be noted thatthe thick fourth spacer layer 560 can be deposited or grown usingdeposition techniques that are well known in the art and are notdescribed in detail herein.

[0054] The thick fourth spacer layer 560 is etched a first time to formthe structure illustrated in FIG. 5h. In one embodiment, this etch is ananisotropic (directional) etch which will remove nitride, but not oxide.Examples of anisotropic etches are a dry etch or a plasma etch.

[0055] The thick fourth spacer layer 560 is then recessed by etching asecond time to form the spacer structure illustrated in FIG. 5i. In oneembodiment, the thick fourth spacer layer 560 is etched approximately 60nm deeper than the surface level of the gate layer 520. In oneembodiment, this etch is an isotropic (multidirectional) etch which willremove nitride, but not oxide. Examples of isotropic etches are wet ordry etches.

[0056] The thin Bird spacer layer 550 is then recessed by etching toform the spacer structure illustrated in FIG. 5j. In one embodiment,this etch is an isotropic (multidirectional) etch which will removeoxide, but not nitride. Examples of isotropic etches are a dry, wet orchemical bath etch.

[0057] In FIG. 5k, a reactant layer 570 is deposited, for example, bysputter, electron beam evaporation, chemical vapor, or plasmadeposition. In one embodiment, the reactant layer 570 can be a metalsuch as titanium.

[0058] The reactant layer 570 and the gate layer 520 are then annealedto form a conductive layer 580 as shown in FIG. 5l. In one embodiment,the conductive layer 580 can be a polycide, such as titanium salicide.In one embodiment, the anneal may be performed using a rapid thermalannealing process in a nitrogen ambient. In one embodiment, additionalanneals can be performed to decrease the resistance of the conductivelayer 580. It is to be noted that the conductive layer 580 can nowextend beyond the edges of the gate layer 520 due to flexibility in thethin spacer walls formed from the thin first spacer layer 530 and thethin second spacer layer 540.

[0059] The unreacted reactant layer 570 is etched away leaving theconductive layer 580 as illustrated in FIG. 5m. In one embodiment, thisetch is an isotropic etch which will remove unreacted titanium, but nottitanium salicide.

[0060] Another embodiment of the present invention is illustrated inFIGS. 6a-p. FIG. 6a illustrates a gate layer 620 formed on a thininsulative layer 610 on a substrate 600. In one embodiment, the gatelayer 620 can be polysilicon. In one embodiment, the gate layer 620 isless than 0.20 μm in width. These structures are formed usingconventional deposition and etching techniques well-known in the art.

[0061] In FIG. 6b, a thin first spacer layer 630 is deposited or grownon the gate layer 620 and substrate 600. In one embodiment, the thinfirst spacer layer 630 can be an oxide. In one embodiment, the thinfirst spacer layer 630 is deposited or grown to a thickness in the rangeof approximately 50 -150 Å, for example, 50 Å. It should be noted thatthe thin first spacer layer 630 can be deposited or grown usingdeposition techniques that are well known in the art and are notdescribed in detail herein.

[0062] In FIG. 6c, a thin second spacer layer 640 is deposited or grownon the thin first spacer layer 630. In one embodiment, the thin secondspacer layer 640 can be a nitride. In one embodiment, the thin secondspacer layer 640 can be deposited or grown to a thickness in the rangeof approximately 50-150 Å, for example, 50 Å. It should be noted thatthe thin second spacer layer 640 can be deposited or grown usingdeposition techniques that are well known in the art and are notdescribed in detail herein.

[0063] The thin second spacer layer 640 is etched a first time to formthe structure illustrated in FIG. 6d. In one embodiment, this etch is ananisotropic (directional) etch which will remove nitride, but not oxide.Examples of anisotropic etches are a dry etch or a plasma etch.

[0064] Following the etch of the thin second spacer layer 640, the thinfirst spacer layer 630 is etched to form the structure illustrated inFIG. 6e. In one embodiment, this etch is an isotropic (multidirectional)which will attack oxide, but not nitride. Examples of isotropic etchesare a dry, wet or chemical bath etch. It should be further noted that atthis point in a process flow, implants of dopants can be added to thestructure to enhance circuit performance.

[0065] In FIG. 6f, a thin third spacer layer 650 is deposited or grown.In one embodiment, the thin third spacer layer 650 can be an oxide. Inone embodiment, the thin third spacer layer 650 is deposited or grown toa thickness in the range of approximately 50-300 Å, for example 100 Å.It should be noted that the thin third spacer layer 650 can be depositedor grown using deposition techniques that are well known in the art andare not described in detail herein.

[0066] In FIG. 6g, a thick fourth spacer layer 660 is deposited or grownon the thin third spacer layer 650. In one embodiment, the thick fourthspacer layer 660 can be a nitride. In one embodiment, the thick fourthspacer layer 660 is deposited or grown to a thickness in the range ofapproximately 300 -2000 Å, for example, 800 Å. It should be noted thatthe thick fourth spacer layer 660 can be deposited or grown usingdeposition techniques that are well known in the art and are notdescribed in detail herein.

[0067] The thick fourth spacer layer 660 is etched a first time to formthe structure illustrated in FIG. 6h. In one embodiment, this etch is ananisotropic (directional) etch which will remove nitride, but not oxide.Examples of anisotropic etches are a dry etch or a plasma etch.

[0068] The thick fourth spacer layer 660 is then recessed by etching asecond time to form the spacer structure illustrated in FIG. 6i. In oneembodiment, the thick fourth spacer layer 660 is etched approximately 60nm deeper than the surface level of the gate layer 620. In oneembodiment, this etch is an isotropic (multidirectional) etch which willremove nitride, but not oxide. Examples of isotropic etches are a wet ordry etch.

[0069] The thin third spacer layer 650 is then recessed by etching toform the spacer structure illustrated in FIG. 6j. In one embodiment,this etch is an isotropic (multidirectional) etch which will removeoxide, but not nitride. Examples of isotropic etches are dry or wetetches.

[0070] At this point, further etches are still to be performed, however,the substrate 600 is left exposed. Thus, if a following etch chemistryis utilized which can remove the substrate 600, the substrate 600 willneed to be protected. Thus, a protective layer, for example, an oxidelayer, can be provided. The provision of a protective layer is describedtogether with the figures that follow. Alternatively, if a followingetch chemistry does not remove the substrate 600, then the process cancontinue without the necessity of providing and removing a protectivelayer.

[0071] In FIG. 6k, a thin protective layer 670 is deposited or grown onthe substrate 600. In one embodiment, the thin protective layer 670 canbe oxide. In one embodiment, the thin protective layer 670 is depositedor grown to a thickness in the range of approximately 50 -300 Å, forexample, 50 Å. In one embodiment, the thin protective layer 670 can bean oxide grown by annealing a silicon substrate 600 in an oxygenambient.

[0072] The thin second spacer layer 640 is recessed by etching to formthe spacer structure illustrated in FIG. 6l. In one embodiment, thisetch is an anisotropic (directional) etch which will remove nitride, butnot oxide. Examples of anisotropic etches are a dry etch or a plasmaetch.

[0073] The thin protective layer 670 is removed and the thin firstspacer layer 630 recessed by etching a second time to form the spacerstructure illustrated in FIG. 6m. In one embodiment, the thin firstspacer layer 630 is recessed approximately 60 nm deeper than the surfacelevel of the gate layer 620. In one embodiment, this etch is anisotropic (multidirectional) etch which will remove oxide, but notnitride. Examples of isotropic etches are a wet, dry or chemical bathetch. It should be noted that the side walls of the gate layer 620 arenow exposed creating a larger contact (reaction) surface area.

[0074] In FIG. 6n, a reactant layer 680 is deposited, for example, bysputter, electron beam evaporation, chemical vapor, or plasmadeposition. In one embodiment, the reactant layer 680 can be a metal,such as titanium.

[0075] The reactant layer 680 and the gate layer 620 are then annealedto form a conductive layer 690 as shown in FIG. 6o. In one embodiment,the conductive layer 690 can be a polycide, such as titanium salicide.In one embodiment, the anneal may be performed using a rapid thermalannealing process in a nitrogen ambient. In one embodiment, additionalanneals can be performed to decrease the resistance of the conductivelayer 690. It is to be noted that the conductive layer 690 can nowextend beyond the edges of the gate layer 620 and is not constrained andstressed.

[0076] The unreacted reactant layer 680 is etched away leaving theconductive layer 690 as illustrated in FIG. 6p. In one embodiment, thisetch is an isotropic etch which will remove unreacted titanium, but nottitanium salicide.

[0077] Through out the specification, reference has been made toisotropic and anisotropic etching. It should be noted that the presentinvention may be performed using these etch processes interchangeably,however, such interchanging of etch processes may cause othercomplications. The process steps as defined above are the preferredmanner in which to perform the present invention.

[0078] Additionally, throughout the specification, it has been statedthat the etch processes remove only the nitride or oxide layers,however, it should be noted that such etch processes selectively removethe nitride or oxide. In other words, an etch to remove nitride willremove nitride at a faster rate than oxide, such that more nitride isremoved and very little oxide is removed; and, an etch to remove oxidewill remove oxide at a faster rate than nitride, such that more oxide isremoved and very little nitride is removed.

[0079] The above described embodiments of the method and device of thepresent invention provide improved polycide resistance in polysilicongate widths below 0.20 μm. As earlier described, conductive layers, suchas the polycide, titanium salicide, can expand during formation.Previous gate electrode structures had spacer structures whichconstrained this expansion. This led to a stressed conductive layer thatexhibited increased resistance. The several embodiments of the presentinvention, reduce the stress on the formed conductive layer therebyimproving the resistance. In some embodiments, spacers are recessed toremove constraints on the expansion of the conductive layer. In otherembodiments, spacers are partially recessed to provide thin spacer wallswhich flex to dissipate stress. In other embodiments, dual spacer stacksthat are recessed and partially recessed also provide dissipate orremove stress on the conductive layer. It is this reduction in thestress by the several embodiments of the present invention, thatprovides improved resistance. Also, in several of the embodiments theside walls of the gate layer are exposed to allow greater surface area.This aids in formation of the conductive layer by providing forincreased nucleation sites. By aiding in formation of the conductivelayer, process yields increase.

[0080] In the foregoing specification, the invention has been describedwith reference to specific exemplary embodiments thereof. It will,however, be evident that various modifications and changes may be madethereto without departing from the broader spirit and scope of theinvention as set forth in the appended claims. The specification anddrawings are, accordingly, to be regarded in an illustrative rather thana restrictive sense.

What is claimed is:
 1. A gate electrode formed on a substratecomprising: an insulative layer formed on a substrate; a gate layerformed on the insulative layer; a conductive layer formed on the gatelayer; thick first spacers formed adjacent to opposite sides of the gatelayer wherein the thick first spacers are recessed to create a openspace between the both the gate layer and the conductive layer and thicksecond spacers; and, thick second spacers formed adjacent to each of thethick first spacers.
 2. The gate electrode of claim 1 wherein theinsulative layer is an oxide.
 3. The gate electrode of claim 2 whereinthe gate layer is a polysilicon.
 4. The gate electrode of claim 3wherein the conductive layer is a polycide.
 5. The gate electrode ofclaim 4 wherein the thick first spacers are an oxide.
 6. The gateelectrode of claim 5 wherein the thick second spacers are a nitride. 7.The gate electrode of claim 6 wherein the polycide is titanium salicide(TiSi₂).
 8. A gate electrode formed on a substrate comprising: aninsulative layer formed on a substrate; a gate layer formed on theinsulative layer; a conductive layer formed on the gate layer; thinfirst spacers formed adjacent to opposite sides of the gate layerwherein the thin first spacers are recessed; and, thick second spacersformed adjacent to each of the thin first spacers wherein the thicksecond spacers are recessed.
 9. The gate electrode of claim 8 whereinthe insulative layer is an oxide.
 10. The gate electrode of claim 9wherein the gate layer is a polysilicon.
 11. The gate electrode of claim10 wherein the conductive layer is a polycide.
 12. The gate electrode ofclaim 11 wherein the thin first spacers are an oxide.
 13. The gateelectrode of claim 12 wherein the thick second spacers are a nitride.14. The gate electrode of claim 13 wherein the polycide is titaniumsalicide (TiSi₂).
 15. A gate electrode formed on a substrate comprising:an insulative layer formed on a substrate; a gate layer formed on theinsulative layer; a conductive layer formed on the gate layer; thinfirst spacers formed adjacent to opposite sides of the gate layer; and,thick second spacers formed adjacent to each of the thin first spacerswherein the thick second spacers are partially recessed to form thinsecond spacer walls adjacent to the thin first spacers in a regionadjacent to the conductive layer.
 16. The gate electrode of claim 15wherein the insulative layer is an oxide.
 17. The gate electrode ofclaim 16 wherein the gate layer is a polysilicon.
 18. The gate electrodeof claim 17 wherein the conductive layer is a polycide.
 19. The gateelectrode of claim 18 wherein the thin first spacers are an oxide. 20.The gate electrode of claim 19 wherein the thick second spacers are anitride.
 21. The gate electrode of claim 20 wherein the polycide istitanium salicide (TiSi₂).
 22. A gate electrode formed on a substratecomprising: an insulative layer formed on a substrate; a gate layerformed on the insulative layer; a conductive layer formed on the gatelayer; thin first spacers formed adjacent to opposite sides of the gatelayer; thin second spacers formed adjacent to each of the thin firstspacers; thin third spacers formed adjacent to each of the thin secondspacers wherein the thin third spacers are recessed; and, thick fourthspacers formed adjacent to each of the thin third spacers wherein thethick fourth spacers are recessed.
 23. The gate electrode of claim 22wherein the insulative layer is an oxide.
 24. The gate electrode ofclaim 23 wherein the gate layer is a polysilicon.
 25. The gate electrodeof claim 24 wherein the conductive layer is a polycide.
 26. The gateelectrode of claim 25 wherein the thin first spacers are an oxide. 27.The gate electrode of claim 26 wherein the thin second spacers are anitride.
 28. The gate electrode of claim 27 wherein the thin thirdspacers are an oxide.
 29. The gate electrode of claim 28 wherein thethick fourth spacers are a nitride.
 30. The gate electrode of claim 29wherein the polycide is titanium salicide (TiSi₂).
 31. A gate electrodeformed on a substrate comprising: an insulative layer formed on asubstrate; a gate layer formed on the insulative layer; a conductivelayer formed on the gate layer; thin first spacers formed adjacent toopposite sides of the gate layer wherein the thin first spacers arerecessed; thin second spacers formed adjacent to opposite sides of thethin first spacers wherein the thin second spacers are recessed; thinthird spacers formed adjacent to opposite sides of the thin secondspacers wherein the thin third spacers are recessed; and, thick fourthspacers formed adjacent to opposite sides of the thin third spacerswherein the thick fourth spacers are recessed.
 32. The gate electrode ofclaim 31 wherein the insulative layer is an oxide.
 33. The gateelectrode of claim 32 wherein the gate layer is a polysilicon.
 34. Thegate electrode of claim 33 wherein the conductive layer is a polycide.35. The gate electrode of claim 34 wherein the thin first spacers are anoxide.
 36. The gate electrode of claim 35 wherein the thin secondspacers are a nitride.
 37. The gate electrode of claim 36 wherein thethin third spacers are an oxide.
 38. The gate electrode of claim 37wherein the thick fourth spacers are a nitride.
 39. The gate electrodeof claim 38 wherein the polycide is titanium salicide (TiSi₂).
 40. Amethod for forming a gate electrode comprising the steps of: providing asubstrate with an insulative layer deposited thereon; forming a gatelayer on the insulative layer; depositing a thick first spacer layer onthe gate layer and the substrate; depositing a thick second spacer layeron the thick first spacer layer; removing a portion of the thick secondspacer layer to form thick second spacers adjacent to the thick firstspacer layer; removing a portion of the thick first spacer layer to formrecessed thick first spacers adjacent to the gate layer wherein a spaceis formed between the gate layer and the thick second spacers;depositing a layer of reactant on the gate layer; annealing the layer ofreactant and the gate layer to form a conductive layer; and, removingthe unreacted reactant layer.
 41. The method of claim 40 whereinremoving a portion of the thick second spacer layer to form thick secondspacers is by anisotropic etching.
 42. The method of claim 41 whereinthe removing a portion of the thick first spacer layer to form thickfirst spacers is by isotropic etching.
 43. The method of claim 42wherein the insulative layer is an oxide.
 44. The method of claim 43wherein the gate layer is a polysilicon.
 45. The method of claim 44wherein the reactant is a metal.
 46. The method of claim 45 wherein saidthick first spacer layer is an oxide.
 47. The method of claim 46 whereinsaid thick second spacer layer is a nitride.
 48. The method of claim 47wherein the conductive layer is a polycide.
 49. The method of claim 48wherein the metal is titanium.
 50. The method of claim 49 wherein thepolycide is titanium salicide (TiSi₂).
 51. A method for forming a gateelectrode comprising the steps of: providing a substrate with a gateoxide layer deposited thereon; forming a gate layer on the insulativelayer; depositing a thin first spacer layer on the gate layer and thesubstrate; depositing a thick second spacer layer on the thin firstspacer layer; removing a portion of the thick second spacer layer toform recessed thick second spacers; removing a portion of the thin firstspacer layer to form recessed thin first spacers; depositing a layer ofreactant on the gate layer; annealing the layer of reactant and the gatelayer to form a conductive layer; and, removing the unreacted reactantlayer.
 52. The method of claim 51 wherein removing a portion of thethick second spacer layer to form thick second spacers is by anisotropicetching.
 53. The method of claim 52 wherein the removing a portion ofthe thin first spacer layer to form thin first spacers is by isotropicetching.
 54. The method of claim 53 wherein the insulative layer is anoxide.
 55. The method of claim 54 wherein the gate layer is apolysilicon.
 56. The method of claim 55 wherein the reactant is a metal.57. The method of claim 56 wherein said thin first spacer layer is anoxide.
 58. The method of claim 57 wherein said thick second spacer layeris a nitride.
 59. The method of claim 58 wherein the conductive layer isa polycide.
 60. The method of claim 59 wherein the metal is titanium.61. The method of claim 60 wherein the polycide is titanium salicide(TiSi₂).
 62. A method for forming a gate electrode comprising the stepsof: providing a substrate with an insulative layer deposited thereon;forming a gate layer on the insulative layer; depositing a thin firstspacer layer on the gate layer and the substrate; depositing a thicksecond spacer layer on the thin first spacer layer; removing a portionof the thick second spacer layer to form partially recessed thick secondspacers; removing a portion of the thin first spacer layer to form thinfirst spacers; depositing a layer of reactant on the gate layer;annealing the layer of reactant and the gate layer to form a conductivelayer; and, removing the unreacted reactant layer.
 63. The method ofclaim 62 wherein removing a portion of the thick second spacer layer toform partially recessed thick second spacers further comprises: removinga first portion of the thick second spacer by anisotropic etching; and,removing a second portion of the thick second spacer layer by isotropicetching to form thin second spacer walls adjacent to the thin firstspacers and in a region adjacent to the conductive layer.
 64. The methodof claim 63 wherein removing a portion of the thin first spacer layer toform thin first spacers is by anisotropic etching.
 65. The method ofclaim 64 wherein the insulative layer is an oxide.
 66. The method ofclaim 65 wherein the gate layer is a polysilicon.
 67. The method ofclaim 66 wherein the reactant is a metal.
 68. The method of claim 67wherein said thin first spacer layer is an oxide.
 69. The method ofclaim 68 wherein said thick second spacer layer is a nitride.
 70. Themethod of claim 69 wherein the conductive layer is a polycide.
 71. Themethod of claim 70 wherein the metal is titanium.
 72. The method ofclaim 71 wherein the polycide is titanium salicide (TiSi₂).
 73. A methodfor forming a gate electrode comprising the steps of: providing asubstrate with an insulative layer deposited thereon; forming a gatelayer on the insulative layer; depositing a thin first spacer layer onthe gate layer and the substrate; depositing a thin second spacer layeron the thin first spacer layer; removing a portion of the thin secondspacer layer to form thin second spacers; removing a portion of the thinfirst spacer layer to form thin first spacers; depositing a thin thirdspacer layer; depositing a thick fourth spacer layer on the thin thirdspacer layer; removing a portion of the thick fourth spacer layer toform recessed thick fourth spacers; removing a portion of the thin thirdspacer layer to form recessed thin third spacers; depositing a layer ofreactant on the gate layer; annealing the layer of reactant and the gatelayer to form a conductive layer; and, removing the unreacted reactantlayer.
 74. The method of claim 73 wherein removing a portion of the thinsecond spacer layer to form thin second spacers is by anisotropicetching.
 75. The method of claim 74 wherein removing a portion of thethin first spacer layer to form thin first spacers is by anisotropicetching.
 76. The method of claim 75 wherein removing a portion of thethick fourth spacer layer to form recessed thick fourth spacers furthercomprises: removing a first portion of the thick fourth spacer layer byanisotropic etching; and, removing a second portion of the thick fourthspacer by isotropic etching.
 77. The method of claim 76 wherein removinga portion of the thin third spacer layer to form recessed thin thirdspacers is by anisotropic etching.
 78. The method of claim 77 whereinthe insulative layer is an oxide.
 79. The method of claim 78 wherein thegate layer is a polysilicon.
 80. The method of claim 79 wherein thereactant is a metal.
 81. The method of claim 80 wherein said thin firstspacer layer is an oxide.
 82. The method of claim 81 wherein said thinsecond spacer layer is a nitride.
 83. The method of claim 82 whereinsaid thin third spacer layer is an oxide.
 84. The method of claim 83wherein said thick fourth spacer layer is a nitride.
 85. The method ofclaim 84 wherein the conductive layer is a polycide.
 86. The method ofclaim 85 wherein the metal is titanium.
 87. The method of claim 86wherein the polycide is titanium salicide (TiSi₂).
 88. A method forforming a gate electrode comprising the steps of: providing a substratewith an insulative layer deposited thereon; forming a gate layer on theinsulative layer; depositing a thin first spacer layer on the gate layerand the substrate; depositing a thin second spacer layer on the thinfirst spacer layer; removing a portion of the thin second spacer layerto form thin second spacers; removing a portion of the thin first spacerlayer to form thin first spacers; depositing a thin third spacer layer;depositing a thick fourth spacer layer on the thin third spacer layer;removing a portion of the thick fourth spacer layer to form recessedthick fourth spacers; removing a portion of the thin third spacer layerto form recessed third spacers; forming a protective layer on thesubstrate and gate layer; removing a portion of the thin second spacersto form recessed thin second spacers; removing the protective layer andremoving a portion of the thin first spacers to form recessed thin firstspacers; depositing a layer of reactant on the gate layer; annealing thelayer of reactant and the gate layer to form a conductive layer; and,removing the unreacted reactant layer.
 89. The method of claim 88wherein removing a portion of the thin second spacer layer to form thinsecond spacers is by anisotropic etching.
 90. The method of claim 89wherein removing a portion of the thin first spacer layer to form thinfirst spacers is by anisotropic etching.
 91. The method of claim 90wherein removing a portion of the thick fourth spacer layer to formrecessed thick fourth spacers further comprises: removing a firstportion of the thick fourth spacer layer by anisotropic etching; and,removing a second portion of the thick fourth spacer layer by isotropicetching.
 92. The method of claim 91 wherein removing a portion of thethin third spacer layer to form recessed thin third spacers is byanisotropic etching.
 93. The method of claim 92 wherein removing aportion of the thin second spacers to form recessed thin second spacersis by isotropic etching.
 94. The method of claim 93 wherein removing theprotective layer and removing a portion of the thin first spacers toform recessed thin first spacers is by isotropic etching.
 95. The methodof claim 94 wherein the insulative layer is an oxide.
 96. The method ofclaim 95 wherein the gate layer is a polysilicon.
 97. The method ofclaim 96 wherein the reactant is a metal.
 98. The method of claim 97wherein the thin first spacer layer is an oxide.
 99. The method of claim98 wherein the thin second spacer layer is a nitride.
 100. The method ofclaim 99 wherein the thin third spacer layer is an oxide.
 101. Themethod of claim 100 wherein the thick fourth spacer layer is a nitride.102. The method of claim 101 wherein the protective layer is an oxide.103. The method of claim 101 wherein the conductive layer is a polycide.104. The method of claim 102 wherein the metal is titanium.
 105. Themethod of claim 103 wherein the polycide is titanium salicide (TiSi₂).106. A method for forming a gate electrode comprising the steps of:providing a substrate with an insulative layer deposited thereon;forming a gate layer on the insulative layer; depositing a thin firstspacer layer on the gate layer and the substrate; depositing a thinsecond spacer layer on the thin first spacer layer; removing a portionof the thin second spacer layer to form thin second spacers; removing aportion of the thin first spacer layer to form thin first spacers;depositing a thin third spacer layer; depositing a thick fourth spacerlayer on the thin third spacer layer; removing a portion of the thickfourth spacer layer to form recessed thick fourth spacers; removing aportion of the thin third spacer layer to form recessed third spacers;removing a portion of the thin second spacers to form recessed thinsecond spacers; removing a portion of the thin first spacers to formrecessed thin first spacers; depositing a layer of reactant on the gatelayer; annealing the layer of reactant and the gate layer to form aconductive layer; and, removing the unreacted reactant layer.
 107. Themethod of claim 105 wherein removing a portion of the thin second spacerlayer to form thin second spacers is by anisotropic etching.
 108. Themethod of claim 106 wherein removing a portion of the thin first spacerlayer to form thin first spacers is by anisotropic etching.
 109. Themethod of claim 107 wherein removing a portion of the thick fourthspacer layer to form recessed thick fourth spacers further comprises:removing a first portion of the thick fourth spacer layer by anisotropicetching; and, removing a second portion of the thick fourth spacer layerby isotropic etching.
 110. The method of claim 108 wherein removing aportion of the thin third spacer layer to form recessed thin thirdspacers is by anisotropic etching.
 111. The method of claim 109 whereinremoving a portion of the thin second spacers to form recessed thinsecond spacers is by isotropic etching.
 112. The method of claim 110wherein removing a portion of the thin first spacers to form recessedthin first spacers is by isotropic etching.
 113. The method of claim 111wherein the insulative layer is an oxide.
 114. The method of claim 112wherein the gate layer is a polysilicon.
 115. The method of claim 113wherein the reactant is a metal.
 116. The method of claim 114 whereinthe thin first spacer layer is an oxide.
 117. The method of claim 115wherein the thin second spacer layer is a nitride.
 118. The method ofclaim 116 wherein the thin third spacer layer is an oxide.
 119. Themethod of claim 117 wherein the thick fourth spacer layer is a nitride.120. The method of claim 118 wherein the conductive layer is a polycide.121. The method of claim 119 wherein the metal is titanium.
 122. Themethod of claim 120 wherein the polycide is titanium salicide (TiSi₂).